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ff3:ff3us:doc:snes:register [2019/08/03 03:37] madsiur [Video Port Control] |
ff3:ff3us:doc:snes:register [2019/08/08 02:28] madsiur [Counter Latch] |
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Line 55: | Line 55: | ||
|Window Area Main Screen Disable | |Window Area Main Screen Disable | ||
|Window Area Subscreen Disable | |Window Area Subscreen Disable | ||
- | |Color Math Registers | + | |Color Math Control Register A |
- | |Color Math Registers | + | |Color Math Control Register B |
- | |Color Math Registers | + | |Color Math Subscreen Backdrop Color |
- | |Screen Mode Select | + | |Screen Mode / Video Select |
- | |Multiplication | + | |Signed Multiply |
- | |Multiplication | + | |Signed Multiply |
- | |Multiplication | + | |Signed Multiply |
- | |Software | + | |Latch |
- | |OAM Data Read Register | + | |OAM Data Read | |
- | |VRAM Data Read Register | + | |VRAM Data Read (Low) | |
- | |VRAM Data Read Register | + | |VRAM Data Read (High) |
- | |CGRAM Data Read Register | + | |CGRAM Data Read | |
- | |Scanline Location Registers (Horizontal) | + | |Horizontal |
- | |Scanline Location Registers (Vertical) | + | |Vertical |
|PPU Status Register | |PPU Status Register | ||
|PPU Status Register | |PPU Status Register | ||
Line 181: | Line 181: | ||
x = Forced Blanking (0=Normal, 1=Screen Black) | x = Forced Blanking (0=Normal, 1=Screen Black) | ||
- | uuu = Unused | + | uuu = unused |
bbbb = Master Brightness (0=Screen Black, or N=1..15: Brightness*(N+1)/ | bbbb = Master Brightness (0=Screen Black, or N=1..15: Brightness*(N+1)/ | ||
</ | </ | ||
Line 223: | Line 223: | ||
puuuuuub aaaaaaaa | puuuuuub aaaaaaaa | ||
p = OAM Priority Rotation | p = OAM Priority Rotation | ||
- | uuuuuu | + | uuuuuu |
baaaaaaaa | baaaaaaaa | ||
aaaaaaa | aaaaaaa | ||
Line 360: | Line 360: | ||
$210E ww+++- BG1VOFS | $210E ww+++- BG1VOFS | ||
| | ||
- | | + | |
- | | + | |
+ | nnnnnn | ||
xxxxxxxxxx | xxxxxxxxxx | ||
+ | uuu = unused | ||
mmmmmmmmmmmmm = The Mode 7 BG offset, 13 bits two' | mmmmmmmmmmmmm = The Mode 7 BG offset, 13 bits two' | ||
</ | </ | ||
Line 380: | Line 382: | ||
$2113 ww+++- BG4HOFS | $2113 ww+++- BG4HOFS | ||
$2114 ww+++- BG4VOFS | $2114 ww+++- BG4VOFS | ||
- | | + | |
+ | uuuuu = unused | ||
xxxxxxxxxx = The BG offset, 10 bits | xxxxxxxxxx = The BG offset, 10 bits | ||
</ | </ | ||
Line 655: | Line 658: | ||
Allows to disable video layers within the window region. " | Allows to disable video layers within the window region. " | ||
+ | |||
+ | [[register# | ||
+ | |||
+ | ===== Color Math Control Register A ===== | ||
+ | < | ||
+ | $2130 wb+++- CGWSEL - Color Addition Select | ||
+ | ccmmuusd | ||
+ | cc = Clip colors to black before math (Force Main Screen Black) | ||
+ | 00 = Never | ||
+ | 01 = Outside Color Window only (NotMathWindow) | ||
+ | 02 = Inside Color Window only (MathWindow) | ||
+ | 03 = Always | ||
+ | mm = Color Math Enable | ||
+ | 00 = Never | ||
+ | 01 = Outside Color Window only (NotMathWindow) | ||
+ | 02 = Inside Color Window only (MathWindow) | ||
+ | 03 = Always | ||
+ | uu = unused | ||
+ | s = Subscreen BG/OBJ Enable (0=No/ | ||
+ | d = Direct Color (for 256-color BGs) (0=Use Palette, 1=Direct Color) | ||
+ | </ | ||
+ | |||
+ | [[register# | ||
+ | |||
+ | ===== Color Math Control Register B ===== | ||
+ | < | ||
+ | 2131 wb+++- CGADSUB - Color math designation | ||
+ | shbo4321 | ||
+ | s = Color Math Add/ | ||
+ | h = Color Math " | ||
+ | b = Color Math when Main Screen = Backdrop (0=Off, 1=On) (Off: Show Raw Main, On: Show Main +/- Sub) | ||
+ | o = Color Math when Main Screen = OBJ/ | ||
+ | - = Color Math when Main Screen = OBJ/ | ||
+ | 4 = Color Math when Main Screen = BG4 (0=Off, 1=On) (Off: Show Raw Main, On: Show Main +/- Sub) | ||
+ | 3 = Color Math when Main Screen = BG3 (0=Off, 1=On) (Off: Show Raw Main, On: Show Main +/- Sub) | ||
+ | 2 = Color Math when Main Screen = BG2 (0=Off, 1=On) (Off: Show Raw Main, On: Show Main +/- Sub) | ||
+ | 1 = Color Math when Main Screen = BG1 (0=Off, 1=On) (Off: Show Raw Main, On: Show Main +/- Sub) | ||
+ | </ | ||
+ | |||
+ | Half-Color (bit h): Ignored if "Force Main Screen Black" ($2130) is used, also ignored on transparent Subscreen pixels (those use the fixed color as sub-screen backdrop without division) (whilst $2130 (bit s) uses the fixed color as non-transparent one, which allows division). | ||
+ | |||
+ | Bit 1, 2, 3, 4, o, b: Affect MAIN SCREEN layers, id disable, display RAW Main Screen as such (without math) (i.e. $212C enables the main screen, $2131 selects if math is applied on it) | ||
+ | |||
+ | [[register# | ||
+ | |||
+ | ===== Color Math Subscreen Backdrop Color ===== | ||
+ | < | ||
+ | $2132 wb+++- COLDATA - Fixed Color Data | ||
+ | bgrccccc | ||
+ | b = Apply Blue (0=No change, 1=Apply Intensity as Blue) | ||
+ | g = Apply Green (0=No change, 1=Apply Intensity as Green) | ||
+ | r = Apply Red (0=No change, 1=Apply Intensity as Red) | ||
+ | ccccc = Intensity (0..31) | ||
+ | </ | ||
+ | |||
+ | The Subscreen Backdrop Color is used when all sub screen layers are disabled or transparent, | ||
+ | |||
+ | [[register# | ||
+ | |||
+ | ===== Screen Mode / Video Select ===== | ||
+ | < | ||
+ | $2133 wb+++- SETINI - Screen Mode/Video Select | ||
+ | seuupoIi | ||
+ | s = External Synchronization (0=Normal, 1=Super Impose and etc.) | ||
+ | e = EXTBG Mode (Screen expand) | ||
+ | uu = unused | ||
+ | p = Horizontal Pseudo 512 Mode (0=Disable, 1=Enable) (shift Subscreen half dot to the left) | ||
+ | o = BG V-Direction Display (0=224 Lines, 1=239 Lines) (for NTSC/PAL) | ||
+ | I = OBJ V-Direction Display (0=Low, 1=High Resolution/ | ||
+ | i = V-Scanning (0=Non Interlace, 1=Interlace) (See Port $2105) | ||
+ | </ | ||
+ | |||
+ | Bit s: Used for superimposing " | ||
+ | |||
+ | Bit e: When this bit is set, you may enable BG2 on Mode 7. BG2 uses the same tile and character data as BG1, but interprets the high bit of the color data as a priority for the pixel. Various sources report additional effects for this bit, possibly related to bit 7. For example, " | ||
+ | |||
+ | Bit p: This creates a 512-pixel horizontal resolution by taking pixels from the Subscreen for the even-numbered pixels (zero based) and from the main screen for the odd-numbered pixels. Color math behaves just as with Mode 5/6 hires. The interlace bit still has no effect. Mosaic operates as normal (not like Mode 5/6). The Subscreen pixel is clipped (by windows) when the main-screen pixel to the LEFT is clipped, not when the one to the RIGHT is clipped as you'd expect. What happens with pixel column 0 is unknown. Enabling this bit in Modes 5 or 6 has no effect. | ||
+ | |||
+ | Bit o: When set, 239 lines will be displayed instead of the normal 224. This also means V-Blank will occur that much later, and be shorter. All that happens is that extra lines get added to the display, and it seems the TV will like to move the display up 8 pixels. Overscan: The bit only matters at the very end of the frame, if you change the setting on line 0xE0 before the normal NMI trigger point then it's the same as if you had it on all frame. Note that this affects both the NMI trigger point and when HDMA stops for the frame. If you turn the bit off at the very beginning of scanline X (for 0xE1< | ||
+ | |||
+ | Bit I: When set regardless of BG mode, the OBJ will be interlaced (see bit 0 below), and thus will appear half-height. Note that this only controls whether obj are drawn as normal or not, the interlace signal is only output to the TV based on bit 0 below. | ||
+ | |||
+ | Bit i: When set in BG mode 5 (and probably 6), the effective screen height will be 448 (or 478) pixels, rather than 224 (or 239). When set in any other mode, the screen will just get a bit jumpy. However, toggling the tilemap each field would simulate the increased screen height (much like pseudo-hires simulares hires). In hardware, setting this bit makes the SNES output a normal interlace signal rather than always forcing one frame. | ||
+ | |||
+ | [[register# | ||
+ | |||
+ | ===== Signed Multiply Result ===== | ||
+ | < | ||
+ | $2134 r l+++? MPYL - Signed Multiplication Result low byte | ||
+ | $2135 r m+++? MPYM - Signed Multiplication Result middle byte | ||
+ | $2136 r h+++? MPYH - Signed Multiplication Result high byte | ||
+ | xxxxxxxx xxxxxxxx xxxxxxxx = Signed Multiplication Result | ||
+ | </ | ||
+ | |||
+ | This is the 2's compliment product of the 16-bit value written to $211B and the 8-bit value most recently written to $211C. There is supposedly no important delay. It may not be operative during Mode 7 rendering. | ||
+ | |||
+ | [[register# | ||
+ | |||
+ | ===== Latch H/V-Counter by Software ===== | ||
+ | < | ||
+ | $2137 b++++ SLHV - Software Latch for H/V Counter | ||
+ | uuuuuuuu = unused (CPU Open Bus; usually last opcode) | ||
+ | </ | ||
+ | |||
+ | Reading from this register latches the current H/V counter values into OPHCT/OPVCT ($213C-$213D) if bit 7 of $2101 is set. The data actually read is open bus. | ||
+ | |||
+ | [[register# | ||
+ | |||
+ | ===== OAM Data Read ===== | ||
+ | < | ||
+ | $2138 r w++?- RDOAM - Data for OAM read | ||
+ | xxxxxxxx = Byte to read from OAM | ||
+ | </ | ||
+ | |||
+ | OAM reads are straightforward: | ||
+ | |||
+ | [[register# | ||
+ | |||
+ | ===== VRAM Data Read ===== | ||
+ | < | ||
+ | $2139 r l++?- RDVRAML - VRAM Data Read low byte | ||
+ | $213A r h++?- RDVRAMH - VRAM Data Read high byte | ||
+ | xxxxxxxx xxxxxxxx = Word to read from VRAM | ||
+ | </ | ||
+ | Reading from these registers returns the LSB or MSB of an internal 16 bit prefetch register. Depending on the Increment Mode the address does (or doesn' | ||
+ | |||
+ | < | ||
+ | Prefetch occurs AFTER changing the VRAM address (by writing $2116-$2117). | ||
+ | Prefetch occurs BEFORE incrementing the VRAM address (by reading $2139-$213A). | ||
+ | </ | ||
+ | |||
+ | The " | ||
+ | |||
+ | < | ||
+ | 1st Send a byte from OLD prefetch value to the CPU (always) | ||
+ | 2nd Load NEW value from OLD address into prefetch register (only if increment occurs) | ||
+ | 3rd Increment address so it becomes the NEW address (only if increment occurs) | ||
+ | </ | ||
+ | |||
+ | Increments caused by writes to $2118-$2119 don't do any prefetching (the prefetch register is left totally unchanged by writes). In practice, after changing the VRAM address (via $2116-$2117), | ||
+ | |||
+ | [[register# | ||
+ | |||
+ | ===== CGRAM Data Read ===== | ||
+ | < | ||
+ | $213B r w++?- RDCGRAM - CGRAM Data read | ||
+ | ubbbbbgg gggrrrrr | ||
+ | u = unused (PPU2 open bus) | ||
+ | bbbbb = Blue Channel | ||
+ | ggggg = Green Channel | ||
+ | rrrrr = Red Channel | ||
+ | </ | ||
+ | |||
+ | This reads from CGRAM. Accesses to CGRAM are handled just like accesses to the low table of OAM, see $2138 for details. Note that the color values are stored in BGR order. After the byte is read, the CGRAM address is incremented so that the next read will be to the following byte. | ||
+ | |||
+ | [[register# | ||
+ | |||
+ | ===== Counter Latch ===== | ||
+ | < | ||
+ | $213C r w++++ OPHCT - Horizontal Counter Latch | ||
+ | $213D r w++++ OPVCT - Vertical Counter Latch | ||
+ | uuuuuuux xxxxxxxx | ||
+ | uuuuuuu | ||
+ | xxxxxxxxx = Scanline Location | ||
+ | </ | ||
+ | |||
+ | These values are latched by reading $2137 when bit 7 of $4201 is set, or by clearing-and-setting bit 7 of $4201 either by writing $4201 or by pin 6 of Controller Port 2 (the latch occurs on the 1->0 transition). Note that the value read is only 9 bits: bits 1-7 of the high byte are PPU2 Open Bus. Each register keeps seperate track of whether to return the low or high byte. The high/low selector is reset to ' | ||
+ | |||
+ | [[register# |