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ff3:ff3us:doc:snes:register [2019/08/06 04:49] madsiur [OAM Data Read] |
ff3:ff3us:doc:snes:register [2019/08/08 02:56] madsiur [Counter Latch] |
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|VRAM Data Read (Low) | [[register# | |VRAM Data Read (Low) | [[register# | ||
|VRAM Data Read (High) | |VRAM Data Read (High) | ||
- | |CGRAM Data Read Register | + | |CGRAM Data Read | |
- | |Scanline Location Registers (Horizontal) | + | |Horizontal |
- | |Scanline Location Registers (Vertical) | + | |Vertical |
- | |PPU Status | + | |PPU1 Status |
- | |PPU Status | + | |PPU2 Status |
|APU IO Registers | |APU IO Registers | ||
|APU IO Registers | |APU IO Registers | ||
Line 778: | Line 778: | ||
===== VRAM Data Read ===== | ===== VRAM Data Read ===== | ||
< | < | ||
- | 2139 r l++?- VMDATALREAD* | + | $2139 r l++?- RDVRAML |
- | 213a r h++?- VMDATAHREAD* | + | $213A r h++?- RDVRAMH |
xxxxxxxx xxxxxxxx = Word to read from VRAM | xxxxxxxx xxxxxxxx = Word to read from VRAM | ||
+ | </ | ||
+ | Reading from these registers returns the LSB or MSB of an internal 16 bit prefetch register. Depending on the Increment Mode the address does (or doesn' | ||
+ | |||
+ | < | ||
+ | Prefetch occurs AFTER changing the VRAM address (by writing $2116-$2117). | ||
+ | Prefetch occurs BEFORE incrementing the VRAM address (by reading $2139-$213A). | ||
+ | </ | ||
+ | |||
+ | The " | ||
+ | |||
+ | < | ||
+ | 1st Send a byte from OLD prefetch value to the CPU (always) | ||
+ | 2nd Load NEW value from OLD address into prefetch register (only if increment occurs) | ||
+ | 3rd Increment address so it becomes the NEW address (only if increment occurs) | ||
+ | </ | ||
+ | |||
+ | Increments caused by writes to $2118-$2119 don't do any prefetching (the prefetch register is left totally unchanged by writes). In practice, after changing the VRAM address (via $2116-$2117), | ||
+ | |||
+ | [[register# | ||
+ | |||
+ | ===== CGRAM Data Read ===== | ||
+ | < | ||
+ | $213B r w++?- RDCGRAM - CGRAM Data read | ||
+ | ubbbbbgg gggrrrrr | ||
+ | u = unused (PPU2 open bus) | ||
+ | bbbbb = Blue Channel | ||
+ | ggggg = Green Channel | ||
+ | rrrrr = Red Channel | ||
+ | </ | ||
+ | |||
+ | This reads from CGRAM. Accesses to CGRAM are handled just like accesses to the low table of OAM, see $2138 for details. Note that the color values are stored in BGR order. After the byte is read, the CGRAM address is incremented so that the next read will be to the following byte. | ||
+ | |||
+ | [[register# | ||
+ | |||
+ | ===== Counter Latch ===== | ||
+ | < | ||
+ | $213C r w++++ OPHCT - Horizontal Counter Latch | ||
+ | $213D r w++++ OPVCT - Vertical Counter Latch | ||
+ | uuuuuuux xxxxxxxx | ||
+ | uuuuuuu | ||
+ | xxxxxxxxx = Scanline Location | ||
+ | </ | ||
+ | |||
+ | These values are latched by reading $2137 when bit 7 of $4201 is set, or by clearing-and-setting bit 7 of $4201 either by writing $4201 or by pin 6 of Controller Port 2 (the latch occurs on the 1->0 transition). Note that the value read is only 9 bits: bits 1-7 of the high byte are PPU2 Open Bus. Each register keeps seperate track of whether to return the low or high byte. The high/low selector is reset to ' | ||
+ | |||
+ | [[register# | ||
+ | |||
+ | ===== PPU1 Status and Version Number ===== | ||
+ | < | ||
+ | $213E r b++++ STAT77 - PPU1 Status and Version Number | ||
+ | trmuvvvv | ||
+ | t = OBJ Time overflow | ||
+ | r = OBJ Range overflow (0=Okay, 1=More than 32 OBJs per scanline) | ||
+ | m = Master/ | ||
+ | u = unused | ||
+ | vvvv = PPU1 5C77 Version Number (only version 1 exists) | ||
+ | </ | ||
+ | |||
+ | Bit t: If more than 34 sprite-tiles (e.g. a 16x16 sprite has 2 sprite-tiles) were encountered on a single line, this flag will be set. The flag is reset at the end of V-Blank but not during forced blank. | ||
+ | |||
+ | Bit r: If more than 32 sprites were encountered on a single line, this flag will be set. The flag is reset at the end of V-Blank but not during forced blank. | ||
+ | |||
+ | Note that the above two flags are set whether or not OBJ are actually enabled at the time (see $212C), at the following times: bit 6 when V=OBJ.YLOC/ |